|
Processor |
CPU Clock |
Voltage |
Internal Register Size |
Data Bus Width |
Max. Memory |
L1 Cache |
L2 Cache |
L3 Cache |
L2/L3 Cache Speed |
Multimedia Instructions |
No. of Transistors |
Date Introduced |
|
Cyrix 6x86 |
2x+ |
2.5–3.5V |
32-bit |
64-bit |
4GB |
16KB |
— |
— |
Bus |
— |
3M |
Feb. '96 |
|
Cyrix 6x86MX/MII |
2x+ |
2.2–2.9V |
32-bit |
64-bit |
4GB |
64KB |
— |
— |
Bus |
MMX |
6.5M |
May '97 |
|
Cyrix III |
2.5x+ |
2.2V |
32-bit |
64-bit |
4GB |
64KB |
256KB |
— |
Core1 |
3DNow! |
22M |
Feb. '00 |
|
NexGen Nx586 |
2x |
4V |
32-bit |
64-bit |
4GB |
2x16KB |
— |
— |
Bus |
— |
3.5M |
Mar. '94 |
|
IDT Winchip |
3x+ |
3.3–3.5V |
32-bit |
64-bit |
4GB |
2x32KB |
— |
— |
Bus |
MMX |
5.4M |
Oct. '97 |
|
IDT Winchip2/2A |
2.33x+ |
3.3–3.5V |
32-bit |
64-bit |
4GB |
2x32KB |
— |
— |
Bus |
3DNow! |
5.9M |
Sep. '98 |
|
Rise mP6 |
2x+ |
2.8V |
32-bit |
64-bit |
4GB |
2x8KB |
— |
— |
Bus |
MMX |
3.6M |
Oct. '98 |
|
VIA C33 |
6x+ |
1.6V |
32-bit |
64-bit |
4GB |
64KB |
128KB |
— |
Bus |
MMX, 3DNow! |
15.2M |
Mar. '01 |
|
VIA C34 |
6x+ |
1.35V |
32-bit |
64-bit |
4GB |
64KB |
128KB |
— |
Bus |
MMX, 3DNow! |
15.4M |
Mar. '01 |
|
VIA C35 |
5.5x+ |
1.35V |
32-bit |
64-bit |
4GB |
64KB |
128KB |
— |
Bus |
MMX, 3DNow! |
15.5M |
Sep. '01 |
|
VIA C36 |
7.5x+ |
1.4V |
32-bit |
64-bit |
4GB |
64KB |
128KB |
— |
Bus |
MMX, 3DNow! |
20.5M |
Jan. '02 |
|
1. L2 cache runs at full-core speed but is contained in a separate chip die. |
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|
2. The Itanium also includes an additional 2MB (150M transistors) or 4MB (300M transistors) of integrated on-cartridge L3 cache running at full-core speed. |
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|
3. Samuel 2 core (improved version of Cyrix III core). |
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|
4. Ezra core. |
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|
5. Ezra-T core. |
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6. Nehemiah core. |
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